1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device having a circuit which generates an internal potential by a charge pump.
2. Description of the Background Art
Recently, semiconductor devices in which a large number of transistors are integrated are used in various electrical equipment, such as workstations and personal computers. Of these semiconductor devices, a DRAM is used as a main memory of personal computers. This DRAM has a charge pump for stetting up power-supply potential. FIG. 11 is a block diagram of a boost circuit contained in a conventional DRAM.
Referring to FIG. 11, the DRAM has a boost circuit 1 normally operating, and a boost circuit 2 that operates when the DRAM is active. Step-up potential V.sub.PP is outputted by the boost circuits 1 and 2. The boost circuit 1 includes a detecting circuit 3 that compares and amplifies reference potential V.sub.REF and input potential V.sub.IN. The input potential V.sub.IN obeys the step-up potential V.sub.PP. The boost circuit 1 further includes a buffering circuit for buffering the output of the detecting circuit 3, a clock generating circuit 5 that outputs a clock signal in response to the output of the buffering circuit 4, and a charge pump 6 driven by the output of the clock generating circuit 5. The charge pump 6 has a low capability of supplying step-up potential V.sub.PP, but has a low power consumption.
The boost circuit 2 comprises a detecting circuit 7 that compares and amplifies reference potential V.sub.REF and input potential V.sub.IN, a buffering circuit 8 for buffering the output of the detecting circuit 7, and an AND gate 9 that receives the output of the buffering circuit 8 and signal ACTL indicating the activation of the DRAM. The signal ACTL reaches its high level when the DRAM is active. The boost circuit 2 further comprises a clock generating circuit 10 that outputs a clock signal in response to the output of the AND gate 9, and a charge pump 11 driven by the output of the clock generating circuit 10. The charge pump 11 has a higher capability of supplying step-up potential V.sub.PP than the charge pump 6.
When the signal ACTL is at its low level indicating the inactive state, from the output of the AND gate 9, a low level is outputted regardless of the detection result of the detecting circuit 7. In response to this low level output, the clock generating circuit 10 stops oscillation of a clock signal. Then, the boost circuit 2 stops step-up operation, and only the boost circuit 1 executes step-up operation.
It is designed so that the detecting circuits 3 and 7 have the same detecting level. However, because of change in process, the detecting circuit 7 can be ahead of the detecting circuit 3 in detecting a decrease in step-up potential V.sub.PP. Such a circuit has caused the following problems. That is, when signal ACTL is at its low level indicating the inactive state, the detecting circuit 7 detects a decrease in step-up potential V.sub.PP whereas the detecting circuit 3 does not detect it in some cases. In this case, both clock generating circuits 5 and 10 stop a clock signal oscillation, and both boost circuits 1 and 2 stop step-up operation. As a result, the output node of the detecting circuit 7 becomes an intermediate potential, and a through current passing through the subsequent buffering circuit 8.